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AN1336 APPLICATION NOTE
Power-Fail Comparator for NVRAM Supervisory Devices
DEALING WITH UNEXPECTED POWER LOSS Inadvertent or unexpected loss of power can cause a number of system level problems. Memory loss, uncontrolled program status and indeterminate processor state are just a few of the issues which can occur during catastrophic power failure. Power-fail recovery is critical for applications created to perform machine control or instrumentation monitoring, therefore knowing the state of the operating system at the time of power loss is very important. The function of the Power Fail Comparator is to provide several milliseconds of early warning that power is failing. This advance warning (see Figure 1) will allow a system to perform operations necessary to prepare for a controlled shutdown sequence. By using a special Power-Fail Input (PFI) to monitor the unregulated supply voltage, a Power Fail Output (PFO) can be generated tPFD after the supply falls below the Power-Fail Threshold (VPFI). This is made possible by the ability of a power supply to continue to function and to provide output power for a period of time after the input power to the power supply has failed. This facility enables the power supply to ride through missing half cycles or missing cycles in an AC supply (see Figure 2 on page 2). Figure 1. Power-Fail Warning
PFI VPFI
tPFD PFO
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Figure 2. Supply Hold-Up
AC Input
Regulated Output Voltage
Power-Fail Warning Power-Fail Output Supply Hold-up
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This is a result of the RC time constant inherent to most power supplies (see Figure 3). This time constant is dominated by capacitors C1 and C3 (C2 is usually quite small). C1 will affect the VUNREG slew rate during power-fail, while C 3 and C1 will more directly affect the regulated Vcc slew rate. Thus when the AC input fails, this capacitance will continue to power the circuit for several milliseconds, typically on the order of 10ms or more. Figure 3. Typical Power Supply
VUNREG REGULATOR VCC C3
C1
C2
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FUNCTIONAL DESCRIPTION An independent bandgap reference comparator is used to monitor the unregulated supply voltage by connecting this supply to the Power-Fail Input pin. The RC time constant of the typical power supply will provide several milliseconds of operating voltage before decaying below a usable value. The Power-Fail Input is constantly compared with an internal voltage reference of 1.25V (see Figure 4). If the input voltage falls below 1.25V, the Power-Fail Output goes low. When it later goes above 1.25V, the output returns high. Adding two external resistors (see Figure 5 on page 4) as a voltage divider circuit allows the comparator to supervise any voltage above 1.25V. The formula to calculate the trip point voltage of PFI (VPFI), which is dependent upon R1 and R2 is:
VTRIP = VPFI (R1 + R2) R2 Where VPFI = 1.25V
Figure 4. Power-Fail Comparator Circuit
PFI
+ PFO 1.25V + - -
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The sum of both resistors should be about 1Mohm to minimize power consumption and to ensure the current in the PFI pin can be neglected compared with the current through the resistor network. The suggested resistor values are shown below (see Table 1). The tolerance of the resistors should not exceed 1% to ensure the sensed voltage does not vary too much. Table 1. Look-up Table for Different Trip Points
R1 (kOhms) 750 910 820 820 1100 R2 (kOhms) 130 130 100 91 100 Vtrip (V) 8.5 10.0 11.5 12.5 15.0
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PFI/PFO OPERATION IN A SYSTEM (HOW DOES IT WORK?) Figure 5. PFI/PFO in a Typical System
9V Regulator AC in 120/240V 50/60HZ AC VUNREG VIN VCC 5V M41ST85Y VCC VOUT RST PFO VPFI R1 PFI R2 ECON INT MCU VCC RST NMI INT SRAM VCC W G E
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A typical power failure can be described by the following three events (see Figure 6): 1. PFI Triggered (t0): As VUNREG falls below the VPFI threshold, PFO is asserted on the MCU's Non-maskable Interrupt (NMI) pin. When NMI is asserted, the MCU halts its current task and begins saving critical data to the NVRAM (safeguard routine). 2. VCC begins to fall (t1): The MCU will continue functioning until the safeguard routine is complete or RESET occurs. 3. RESET Asserted and/or Write Protect occurs (t2): At this point, the MCU needs to have completed the safeguard routine. This results in a safeguard window from PFI to RESET/Write Protect (t2 - t0). Figure 6. Power Failure Sequence
V VUNREG PFI VCC VPFD (t0) Power-Fail Input detected Begin Safeguard Routine (t1) VCC begins to fall (t2) Reset and/or Write Protect (whichever occurs first)
Safeguard Window t t0 t1 t2
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This safeguard window can be used for a number of purposes, depending on the application: Power Save The MCU can switch off, one by one, all non-critical peripheral components to conserve energy for safeguard routines. Data Transfer The MCU may transfer data from the scratch pad memory to the Non-Volatile Memory. It takes only a few MCU cycles if using NVRAM, but can take several milliseconds when this data needs to be stored in an EEPROM or Flash memory. Scratch Pad RAM Over-Write Many applications are now required to run encode/decode algorithms (e.g. DES or RCA) for higher security. Therefore it is sometimes preferable to over-write the working space before power-down to prevent the contents of the RAM from being read illegitimately.
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ADVANTAGES OVER TRADITIONAL POWER MONITORING Typical power monitoring (or supervisory) devices offer features such as brown-out detect by monitoring the voltage at the VCC pin, then asserting a RESET output when VCC drops below a minimum level. Some may also include chip-enable gating or chip-enable write protection which will disable access to the memory, thereby protecting the SRAM contents from errant writes by an MCU that is operating in an undervoltage condition. These are good features and necessary to avoid catastrophic data loss, but unfortunately do not occur early enough to allow the MCU to gracefully enter a fail-safe state. Any of the following scenarios will result in unsatisfactory system shutdown: Loss of Processor State When the RESET occurs, any information not already stored to the NVRAM will be lost. This includes the processor state, the program status, and any information still in the scratch pad RAM, but not in the NVRAM. RESET occurs during a write cycle If the MCU is writing to memory when RESET occurs, that data will most likely be corrupted. This applies to EEPROM and Flash memories as well as NVRAM. Write Protect Occurs before RESET If the NVRAM gates off access to the SRAM prior to processor RESET, the processor may continue accessing/writing the NVRAM expecting that the data written is secure (when it has in fact, been lost).
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HYSTERESIS Hysteresis may be added to PFI for additional noise margin if desired (see Figure 7). The ratio of R1 and R2 should be selected such that PFI sees VPFI when VUNREG falls to its trip point (VTRIP). Connecting R3 between PFI and PFO provides the hysteresis and should typically be more than 10 times the value of R1 or R2. The hysteresis window will extend both above (VH) and below (V L) the original trip point. Figure 7. Adding Hysteresis
VIN PFO R1 VCC PFI R2 C1 R3 VTRIP = VPFI + ( R1R2R2 ) 0V 0V VL VTRIP VH
VIN
1 1 1 ( R1+ R2 + R3 ) V VL = R1 [ VPFI ( 1 + 1 + 1 ) - CC] R1 R2 R3 R3 VH = (VPFI + VPFH ) (R1) PFO GND where VPFI = 1.25V VPFH = 10mV
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TO CONTROLLER
Connecting an ordinary signal diode in series with R3 (see Figure 8) so the lower trip point (VL) to coincides with the trip point without hysteresis, causing the entire hysteresis window to occur above VTRIP. This method provides additional noise margin without compromising the accuracy of the power-fail threshold when the monitored voltage is falling. The current through R1 and R2 should be at least 1A to ensure that the 25nA PFI input current does not shift the trip point. The capacitor C1 is added for noise rejection and should be quite small (e.g., ~100nF), but is optional. Figure 8. Hysteresis on Rising V IN
VIN PFO R1 VCC PFI R2 C1 R3 + ( R1R2R2 ) V VH = R1[(VPFI + VPFH )( 1 + 1 + 1 ) - D ] R1 R2 R3 R3 where VPFI = 1.25V VPFH = 10mV VD = Diode Forward Voltage Drop
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0V 0V VTRIP VH
VIN
VTRIP = VPFI
PFO GND TO CONTROLLER
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Table 2. SUPERVISORY ZEROPOWER/TIMEKEEPER (R) Products with Power-Fail Comparator
Category ZEROPOWER (SZ) TIMEKEEPER (ST) M40SZ100Y, M40SZ100W M48ST59Y/V/W, M48ST37Y/V/W, M41ST85Y/W, M41ST84Y/W Devices
CONTACT INFORMATION If you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses:
apps.nvram@st.com ask.memory@st.com
(for application support) (for general inquiries)
Please remember to include your name, company, location, telephone number, and fax number.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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